The present technology relates to a cache memory. In particular, the technology relates to a cache memory of a set associative type capable of issuing following access without waiting a response to preceding access to a memory, a cache memory control unit, and a method of controlling the cache memory.
A cache memory has been used as a measure of decreasing an access frequency from a processor to a main memory. Such use of the cache memory has been investigated since a degree of reduction in completion time of access to a main memory is smaller than a degree of increase in processing speed of the processor. The main memory is relatively low in cost per unit capacity, but is relatively long in access completion time. In contrast, the cache memory is relatively high in cost per unit capacity, but is relatively short in access completion time. Reduction in cost is achieved together with reduction in access completion time by providing a hierarchized storage mechanism having a cache memory between a processor and a main memory.
Recently, a system including a plurality of processors is becoming a mainstream system among systems including processors. Advancement of hierarchization of the above-described storage mechanism leads to use of a secondary cache or a tertiary cache that may be a storage device shared by a plurality of processors.
When a processor accesses the cache memory, desired data preferably exists on a cache memory. However, the desired data may not actually exist on the cache memory, leading to a cache miss. In such a case, when the cache memory is one stage closer to the processor than a main memory, access from the cache memory to the main memory occurs.
In the case of a cache memory shared by a plurality of processors, there is an issue of how the entire system efficiently performs processing during such access to the main memory until completion of the access without interruption of operation. The following approach may be taken to solve the issue.
(1) When following access to that cache memory results in a cache hit, the processing is continued (hit under miss).
(2) In addition to the (1), when following access to that cache memory results in a cache miss, the processing is also continued (miss under miss).
When such hit under miss or miss under miss is tried to be achieved, access to that cache line is necessary to be suspended until a fill or write-back process due to a cache miss is completed. Therefore, in a previously proposed cache memory, for example, a flag, which indicates whether access is suspended or not, is provided for each cache line in order to suspend that cache line until a fill process is completed (for example, Japanese Unexamined Patent Application Publication Nos. H6-149673 and 2010-033480).